Regviz

Freescale Semiconductor /MKW21Z4 /DCDC /REG3

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as REG3

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MKW21Z4/DCDC/REG3#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)DCDC_VDD1P8CTRL_TRG 0 (0)DCDC_VDD1P5CTRL_TRG_BUCK 0 (0)DCDC_VDD1P5CTRL_TRG_BOOST 0DCDC_VDD1P5CTRL_ADJTN 0 (DCDC_MINPWR_DC_HALFCLK_PULSED)DCDC_MINPWR_DC_HALFCLK_PULSED 0 (DCDC_MINPWR_DOUBLE_FETS_PULSED)DCDC_MINPWR_DOUBLE_FETS_PULSED 0 (DCDC_MINPWR_HALF_FETS_PULSED)DCDC_MINPWR_HALF_FETS_PULSED 0 (DCDC_MINPWR_DC_HALFCLK)DCDC_MINPWR_DC_HALFCLK 0 (DCDC_MINPWR_DOUBLE_FETS)DCDC_MINPWR_DOUBLE_FETS 0 (DCDC_MINPWR_HALF_FETS)DCDC_MINPWR_HALF_FETS 0 (DCDC_VDD1P5CTRL_DISABLE_STEP)DCDC_VDD1P5CTRL_DISABLE_STEP 0 (DCDC_VDD1P8CTRL_DISABLE_STEP)DCDC_VDD1P8CTRL_DISABLE_STEP

DCDC_VDD1P5CTRL_TRG_BOOST=0, DCDC_VDD1P8CTRL_TRG=0, DCDC_VDD1P5CTRL_TRG_BUCK=0

Description

DCDC REGISTER 3

Fields

DCDC_VDD1P8CTRL_TRG

Target value of VDD1P8, 25 mV each step in two ranges, from 0x00 to 0x11 and 0x20 to 0x3F.

0 (0): 1.65 V

6 (110): 1.8 V

17 (10001): 2.075 V

32 (100000): 2.8 V

52 (110100): 3.3 V

63 (111111): 3.575 V
DCDC_VDD1P5CTRL_TRG_BUCK

Target value of VDD1P5 in buck mode, 25 mV each step from 0x00 to 0x0F

0 (0): 1.275 V

9 (1001): 1.5 V

15 (1111): 1.65 V
DCDC_VDD1P5CTRL_TRG_BOOST

Target value of VDD1P5 in boost mode, 25 mV each step from 0x00 to 0x0F

0 (0): 1.275 V

9 (1001): 1.5 V

15 (1111): 1.65 V

21 (10101): 1.8 V
DCDC_VDD1P5CTRL_ADJTN

Adjust value of duty cycle when switching between VDD1P5 and VDD1P8. The unit is 1/32 or 3.125%.
DCDC_MINPWR_DC_HALFCLK_PULSED

Set DCDC clock to half frequency for the Pulsed mode.
DCDC_MINPWR_DOUBLE_FETS_PULSED

Use double switch FET for the Pulsed mode.
DCDC_MINPWR_HALF_FETS_PULSED

Use half switch FET for the Pulsed mode.
DCDC_MINPWR_DC_HALFCLK

Set DCDC clock to half frequency for the continuous mode.
DCDC_MINPWR_DOUBLE_FETS

Use double switch FET for the continuous mode.
DCDC_MINPWR_HALF_FETS

Use half switch FET for the continuous mode.
DCDC_VDD1P5CTRL_DISABLE_STEP

Disable stepping for VDD1P5. Must set this bit before enter low power modes.
DCDC_VDD1P8CTRL_DISABLE_STEP

Disable stepping for VDD1P8. Must set this bit before enter low power modes.

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data